?FPGA設(shè)計(jì)方法培訓(xùn)FPGA Design Methodology課程

Who should attend?

Engineers who seek training for FPGA design best practices that increase design performance and increase development productivity.

Course Outline

• FPGA Design Methodology Checklist
• FPGA Design Methodology
• HDL Coding Techniques
• Reset Methodology
• Lab 1:?Resets
• Lab 2:?SRL and DSP Inference
• Synchronization Circuits and the Clock Interaction Report
• Timing Closure
• FPGA Design Methodology Case Study
• Lab 3:?Timing Closure and Design Conversion
• Course Summary
• Appendix: Timing Constraints Review
• Appendix: Synchronization Circuits and the Clock Interaction Report
• Appendix: Fanout and Logic Replication
• Appendix: Pipelining lab