Vivado Design Suite 的高級(jí)工具和技術(shù)培訓(xùn)課程

Advanced Tools and Techniques of the Vivado Design Suite

Who Should Attend?

Engineers who seek advanced training in using Xilinx tools to improve FPGA performance and utilization while also increasing productivity

Course Outline

?1

• Review of the Vivado Design Suite Static Timing Analysis and Xilinx Design Constraints course
• Design Methodology
• Advanced Timing Analysis
• System-Synchronous I/O Constraints
• Source-Synchronous Constraints
• Lab 1:?Advanced I/O Timing
• Introduction to Pblocks

?2

• Floorplanning Techniques
• Lab 2:?Design Analysis and Floorplanning
• Project-Based and Non-Project Batch Design Flows
• Scripting Using the Project-Based and Non-Project Batch Flows
• Lab 3a:?Scripting in the Project-Based Flow
• Lab 3b:?Scripting in the Non-Project Batch Flow
• Appendix: HDL Coding Techniques